Constant AVOIDED_CHAINING_DELAY_FFS 

pub const AVOIDED_CHAINING_DELAY_FFS: usize = _; // 16_384usize

Flip-flops a naïve 64-stage chaining-value delay would add per lane.

CompressionLane replaces this logical delay with [rhdl_fpga::core::ram::synchronous::SyncBRAM]. Whether the target tools map it to physical block RAM is a synthesis evidence gate.