pub fn try_full_compression_lane_unchecked_verilog() -> Result<String, RHDLError>Expand description
Renders the full lane while deliberately bypassing its final Icarus check.
The pinned RHDL core is patched locally so nested composition consumes raw child descriptors rather than re-running Icarus for every level. Icarus Verilog 13 still overflows its scanner on the monolithic 64-stage function, so callers of this entry point must pass the returned hierarchy through an explicit capable parser such as Verilator or Vivado.
Any successfully returned text would be generation-only evidence. It would not be parse, simulation, equivalence, synthesis, resource, or timing evidence and would still require Verilator and Vivado gates.
ยงErrors
Returns an error if RHDL cannot construct or render the full descriptor.