sha256_rhdl/

farm.rs

//! Parallel SHA-256 compression lanes for the performance profile.
//!
//! [`crate::farm::CompressionFarm`] is the ordinary structural-array reference
//! implementation.  [`crate::farm::ReplicatedCompressionFarm`] makes identical
//! lane configuration explicit so RHDL lowers one child hierarchy and emits
//! multiple hardware instances of it. Every lane receives its own chaining
//! value, block, opaque scheduler tag, and valid bit; every lane returns its own
//! digest, tag, and valid bit. There is no arbiter, runtime hash-profile mux, or
//! input backpressure in either block.
//!
//! [`crate::farm::ThreeLaneCompressionFarm`] is a standalone generation and
//! lane-equivalence target containing three complete 64-round lanes. It accepts
//! up to three unrelated compression blocks per cycle and preserves each
//! lane's exact 64-cycle latency. The production signer does not instantiate
//! this farm: it instantiates one lane inside each of three autonomous
//! four-context clusters. The figures below are architectural projections from
//! the authored RHDL, not synthesis, placement, routing, or hardware evidence.

use rhdl::core::ReplicatedSynchronous;
use rhdl::prelude::*;

use crate::{
    LANE_PIPELINE_FFS, ROUND_COUNT,
    lane::{
        CompressionInput, CompressionLane, CompressionOutput, FULL_LANE_ADDRESS_BITS,
        FULL_LANE_CHAINING_STORAGE_BITS,
    },
};

/// Number of independent compression lanes in the performance farm.
pub const PERFORMANCE_FARM_LANES: usize = 3;

/// Projected round-data, tag, and valid register bits in the full farm.
///
/// This excludes the circular-memory pointers and the registered RAM outputs.
/// It is a source-level count, not a mapped flip-flop count.
pub const THREE_LANE_PROJECTED_PIPELINE_REGISTER_BITS: usize =
    PERFORMANCE_FARM_LANES * LANE_PIPELINE_FFS;

/// Projected circular-memory pointer bits in the full farm.
pub const THREE_LANE_PROJECTED_POINTER_REGISTER_BITS: usize =
    PERFORMANCE_FARM_LANES * FULL_LANE_ADDRESS_BITS;

/// Projected registered synchronous-memory output bits in the full farm.
///
/// A physical implementation may absorb these bits into block-RAM output
/// registers. Only synthesis can determine their mapped resource class.
pub const THREE_LANE_PROJECTED_BRAM_OUTPUT_REGISTER_BITS: usize = PERFORMANCE_FARM_LANES * 8 * 32;

/// Total projected architectural register bits in the full farm.
///
/// This is the arithmetic sum of the pipeline, pointer, and registered-memory
/// output fields authored in RHDL. It must not be reported as FPGA utilization.
pub const THREE_LANE_PROJECTED_ARCHITECTURAL_REGISTER_BITS: usize =
    THREE_LANE_PROJECTED_PIPELINE_REGISTER_BITS
        + THREE_LANE_PROJECTED_POINTER_REGISTER_BITS
        + THREE_LANE_PROJECTED_BRAM_OUTPUT_REGISTER_BITS;

/// Logical chaining-value memory bits in the full farm.
///
/// Whether these 49,152 logical bits infer block RAM, distributed RAM, or
/// registers is a synthesis evidence gate.
pub const THREE_LANE_PROJECTED_CHAINING_MEMORY_BITS: usize =
    PERFORMANCE_FARM_LANES * FULL_LANE_CHAINING_STORAGE_BITS;

const _: () = {
    assert!(THREE_LANE_PROJECTED_PIPELINE_REGISTER_BITS == 153_792);
    assert!(THREE_LANE_PROJECTED_POINTER_REGISTER_BITS == 18);
    assert!(THREE_LANE_PROJECTED_BRAM_OUTPUT_REGISTER_BITS == 768);
    assert!(THREE_LANE_PROJECTED_ARCHITECTURAL_REGISTER_BITS == 154_578);
    assert!(THREE_LANE_PROJECTED_CHAINING_MEMORY_BITS == 49_152);
};

/// Input vector for a farm of `LANES` independent compression pipelines.
pub type CompressionFarmInput<const LANES: usize> = [CompressionInput; LANES];

/// Output vector for a farm of `LANES` independent compression pipelines.
pub type CompressionFarmOutput<const LANES: usize> = [CompressionOutput; LANES];

/// Structural farm of independent SHA-256 compression lanes.
///
/// The farm accepts one input vector on every rising edge. Each element is
/// handled exclusively by the same-index lane and emerges at the same index
/// exactly `ROUNDS` cycles later when not invalidated by reset. A bubble in one
/// lane does not consume capacity in or alter the valid stream of another lane.
/// There is no ready signal and no input backpressure.
///
/// `ROUNDS` and `ADDRESS_BITS` inherit [`CompressionLane`]'s constraints:
/// `ROUNDS` must equal `2^ADDRESS_BITS`, be at least two, and not exceed 64.
#[derive(Clone, Debug, Synchronous, SynchronousDQ)]
#[rhdl(dq_no_prefix)]
pub struct CompressionFarm<const LANES: usize, const ROUNDS: usize, const ADDRESS_BITS: usize>
where
    rhdl::bits::W<ROUNDS>: BitWidth,
    rhdl::bits::W<ADDRESS_BITS>: BitWidth,
{
    lanes: [CompressionLane<ROUNDS, ADDRESS_BITS>; LANES],
}

impl<const LANES: usize, const ROUNDS: usize, const ADDRESS_BITS: usize> Default
    for CompressionFarm<LANES, ROUNDS, ADDRESS_BITS>
where
    rhdl::bits::W<ROUNDS>: BitWidth,
    rhdl::bits::W<ADDRESS_BITS>: BitWidth,
{
    fn default() -> Self {
        assert!(LANES > 0, "a compression farm needs at least one lane");
        Self {
            lanes: core::array::from_fn(|_| CompressionLane::default()),
        }
    }
}

impl<const LANES: usize, const ROUNDS: usize, const ADDRESS_BITS: usize> SynchronousIO
    for CompressionFarm<LANES, ROUNDS, ADDRESS_BITS>
where
    rhdl::bits::W<ROUNDS>: BitWidth,
    rhdl::bits::W<ADDRESS_BITS>: BitWidth,
{
    type I = CompressionFarmInput<LANES>;
    type O = CompressionFarmOutput<LANES>;
    type Kernel = compression_farm_kernel<LANES, ROUNDS, ADDRESS_BITS>;
}

/// Pure structural connectivity for [`CompressionFarm`].
#[kernel]
pub fn compression_farm_kernel<const LANES: usize, const ROUNDS: usize, const ADDRESS_BITS: usize>(
    clock_reset: ClockReset,
    input: CompressionFarmInput<LANES>,
    q: Q<LANES, ROUNDS, ADDRESS_BITS>,
) -> (CompressionFarmOutput<LANES>, D<LANES, ROUNDS, ADDRESS_BITS>)
where
    rhdl::bits::W<ROUNDS>: BitWidth,
    rhdl::bits::W<ADDRESS_BITS>: BitWidth,
{
    let _ = clock_reset;
    let d = D::<LANES, ROUNDS, ADDRESS_BITS> { lanes: input };
    (q.lanes, d)
}

/// Structurally identical SHA-256 compression lanes lowered from one prototype.
///
/// Unlike [`CompressionFarm`], this type promises that every lane has the same
/// configuration. RHDL can therefore lower one [`CompressionLane`] descriptor
/// and instantiate that exact module `LANES` times. Behavioral simulation still
/// allocates independent state per lane, so bubbles, tags, circular-memory
/// pointers, and reset-visible valid bits cannot leak across lane boundaries.
///
/// `LANES` must be positive. `ROUNDS` and `ADDRESS_BITS` inherit
/// [`CompressionLane`]'s constraints: `ROUNDS` must equal
/// `2^ADDRESS_BITS`, be at least two, and not exceed 64.
#[derive(Clone, Debug, Synchronous, SynchronousDQ)]
pub struct ReplicatedCompressionFarm<
    const LANES: usize,
    const ROUNDS: usize,
    const ADDRESS_BITS: usize,
> where
    rhdl::bits::W<ROUNDS>: BitWidth,
    rhdl::bits::W<ADDRESS_BITS>: BitWidth,
{
    lanes: ReplicatedSynchronous<CompressionLane<ROUNDS, ADDRESS_BITS>, LANES>,
}

impl<const LANES: usize, const ROUNDS: usize, const ADDRESS_BITS: usize> Default
    for ReplicatedCompressionFarm<LANES, ROUNDS, ADDRESS_BITS>
where
    rhdl::bits::W<ROUNDS>: BitWidth,
    rhdl::bits::W<ADDRESS_BITS>: BitWidth,
{
    fn default() -> Self {
        Self {
            lanes: ReplicatedSynchronous::new(CompressionLane::default()),
        }
    }
}

impl<const LANES: usize, const ROUNDS: usize, const ADDRESS_BITS: usize> SynchronousIO
    for ReplicatedCompressionFarm<LANES, ROUNDS, ADDRESS_BITS>
where
    rhdl::bits::W<ROUNDS>: BitWidth,
    rhdl::bits::W<ADDRESS_BITS>: BitWidth,
{
    type I = CompressionFarmInput<LANES>;
    type O = CompressionFarmOutput<LANES>;
    type Kernel = replicated_compression_farm_kernel<LANES, ROUNDS, ADDRESS_BITS>;
}

/// Pure structural connectivity for [`ReplicatedCompressionFarm`].
#[kernel]
pub fn replicated_compression_farm_kernel<
    const LANES: usize,
    const ROUNDS: usize,
    const ADDRESS_BITS: usize,
>(
    clock_reset: ClockReset,
    input: CompressionFarmInput<LANES>,
    q: ReplicatedCompressionFarmQ<LANES, ROUNDS, ADDRESS_BITS>,
) -> (
    CompressionFarmOutput<LANES>,
    ReplicatedCompressionFarmD<LANES, ROUNDS, ADDRESS_BITS>,
)
where
    rhdl::bits::W<ROUNDS>: BitWidth,
    rhdl::bits::W<ADDRESS_BITS>: BitWidth,
{
    let _ = clock_reset;
    let d = ReplicatedCompressionFarmD::<LANES, ROUNDS, ADDRESS_BITS> { lanes: input };
    (q.lanes, d)
}

/// Exact three-by-64-round standalone generation and equivalence target.
///
/// This alias demonstrates and validates three independent instances lowered
/// from one repeated prototype. It is not a child of the production signer;
/// that top owns three autonomous clusters, each with its own single shared
/// compression lane.
pub type ThreeLaneCompressionFarm =
    ReplicatedCompressionFarm<PERFORMANCE_FARM_LANES, ROUND_COUNT, FULL_LANE_ADDRESS_BITS>;

/// Emits and Icarus-checks a small farm specialization.
///
/// This function is intended for small lowering-equivalence gates. The pinned
/// RHDL/Icarus path cannot lex the complete 3x64 hierarchy as one monolithic
/// generated source file.
///
/// # Errors
///
/// Returns an error if the specialization is invalid, RHDL lowering fails, or
/// Icarus rejects the generated module hierarchy.
pub fn compression_farm_checked_verilog<
    const LANES: usize,
    const ROUNDS: usize,
    const ADDRESS_BITS: usize,
>() -> Result<String, RHDLError>
where
    rhdl::bits::W<ROUNDS>: BitWidth,
    rhdl::bits::W<ADDRESS_BITS>: BitWidth,
{
    let farm = CompressionFarm::<LANES, ROUNDS, ADDRESS_BITS>::default();
    Ok(farm
        .descriptor("sha256_compression_farm".into())?
        .hdl()?
        .modules
        .pretty())
}

/// Renders the complete three-lane farm while bypassing its final Icarus check.
///
/// The word `unchecked` in this function's name is an evidence warning. The
/// pinned RHDL core is patched locally so nested composition consumes raw child
/// descriptors rather than re-running Icarus for every hierarchy level.
/// Icarus Verilog 13 still overflows its scanner on the monolithic 64-stage
/// functions, so callers must pass the result through a capable parser such as
/// Verilator or Vivado. The returned text alone is only generated-Verilog
/// evidence: it has not been parsed, simulated, proven equivalent, synthesized,
/// placed, routed, timed, or executed on hardware.
///
/// # Errors
///
/// Returns an error if RHDL cannot construct or render the full descriptor.
pub fn try_full_three_lane_farm_generation_only_unchecked_verilog() -> Result<String, RHDLError> {
    let farm = ThreeLaneCompressionFarm::default();
    let descriptor = farm.descriptor("sha256_compression_farm_3x64".into())?;
    let hdl = descriptor.hdl_unchecked()?;
    Ok(hdl.modules.pretty())
}

#[cfg(test)]
mod tests {
    use rhdl::core::sim::ResetOrData;

    use super::*;
    use crate::{
        ROUND_CONSTANTS_RHDL, RoundState, WorkingState, compress_block, feed_forward_kernel,
        round_kernel,
    };

    const SMALL_LANES: usize = PERFORMANCE_FARM_LANES;
    const SMALL_ROUNDS: usize = 4;
    const SMALL_ADDRESS_BITS: usize = 2;

    fn word(value: u32) -> b32 {
        b32(u128::from(value))
    }

    fn word_u32(value: b32) -> u32 {
        let bytes = value.raw().to_le_bytes();
        u32::from_le_bytes([bytes[0], bytes[1], bytes[2], bytes[3]])
    }

    fn prepared_input(lane: usize, marker: u32, sequence: u32) -> CompressionInput {
        let lane = u32::try_from(lane).expect("the three lane indexes fit u32");
        let chaining = core::array::from_fn(|index| {
            let index = u32::try_from(index).expect("eight chaining words fit u32");
            word(
                0x1020_3040_u32
                    .wrapping_add(index.wrapping_mul(0x1111_1111))
                    .rotate_left(index)
                    ^ marker.rotate_right(index)
                    ^ lane.wrapping_mul(0x0101_0101),
            )
        });
        let block = core::array::from_fn(|index| {
            let index = u32::try_from(index).expect("sixteen block words fit u32");
            word(
                marker
                    .wrapping_mul(index.wrapping_add(1))
                    .rotate_left(index * 3)
                    ^ index.wrapping_mul(0x9e37_79b9)
                    ^ lane.rotate_left(index),
            )
        });
        CompressionInput {
            chaining,
            block,
            // The lane byte makes accidental cross-lane delivery obvious.
            tag: word((lane << 24) | (sequence & 0x00ff_ffff)),
            valid: true,
        }
    }

    fn expected_output(input: &CompressionInput, rounds: usize) -> CompressionOutput {
        let digest = if rounds == ROUND_COUNT {
            let chaining = input.chaining.map(word_u32);
            let block = input.block.map(word_u32);
            compress_block(chaining, block).map(word)
        } else {
            let mut state = RoundState {
                working: WorkingState {
                    a: input.chaining[0],
                    b: input.chaining[1],
                    c: input.chaining[2],
                    d: input.chaining[3],
                    e: input.chaining[4],
                    f: input.chaining[5],
                    g: input.chaining[6],
                    h: input.chaining[7],
                },
                schedule: input.block,
            };
            for round_constant in ROUND_CONSTANTS_RHDL.into_iter().take(rounds) {
                state = round_kernel(state, round_constant);
            }
            feed_forward_kernel(input.chaining, state.working)
        };
        CompressionOutput {
            digest,
            tag: input.tag,
            valid: true,
        }
    }

    fn expected_lane_outputs<const LANES: usize>(
        events: &[ResetOrData<CompressionFarmInput<LANES>>],
        lane: usize,
        rounds: usize,
    ) -> Vec<(usize, CompressionOutput)> {
        events
            .iter()
            .enumerate()
            .filter_map(|(accepted_cycle, event)| {
                let ResetOrData::Data(input) = event else {
                    return None;
                };
                let input = input[lane];
                if !input.valid {
                    return None;
                }
                let output_cycle = accepted_cycle + rounds;
                if output_cycle >= events.len()
                    || events[accepted_cycle + 1..output_cycle]
                        .iter()
                        .any(|event| matches!(event, ResetOrData::Reset))
                {
                    return None;
                }
                Some((output_cycle, expected_output(&input, rounds)))
            })
            .collect()
    }

    fn observed_lane_outputs<const LANES: usize, Farm>(
        farm: &Farm,
        events: &[ResetOrData<CompressionFarmInput<LANES>>],
    ) -> [Vec<(usize, CompressionOutput)>; LANES]
    where
        Farm: Synchronous<I = CompressionFarmInput<LANES>, O = CompressionFarmOutput<LANES>>,
    {
        let mut observed = core::array::from_fn(|_| Vec::new());
        for (cycle, sample) in farm
            .run(events.iter().copied().clock_pos_edge(10))
            .synchronous_sample()
            .enumerate()
        {
            for (lane, outputs) in observed.iter_mut().enumerate() {
                if sample.output[lane].valid {
                    outputs.push((cycle, sample.output[lane]));
                }
            }
        }
        observed
    }

    fn all_valid_inputs(sequence: u32, marker: u32) -> CompressionFarmInput<SMALL_LANES> {
        core::array::from_fn(|lane| {
            prepared_input(
                lane,
                marker ^ (u32::try_from(lane).expect("lane fits u32") * 0x1111_1111),
                sequence,
            )
        })
    }

    fn small_farm_events() -> Vec<ResetOrData<CompressionFarmInput<SMALL_LANES>>> {
        let mut events = vec![ResetOrData::Reset];

        // Populate all four circular-memory addresses and all resetless round
        // registers in every lane. Eight cycles also force two pointer wraps.
        events.extend(
            (0..8_u32).map(|cycle| ResetOrData::Data(all_valid_inputs(cycle, 0x1000_0000 + cycle))),
        );

        // Independent valid patterns and unrelated data exercise asymmetric
        // concurrent traffic. The reset kills some but not all lane tokens.
        events.extend([
            ResetOrData::Data(all_valid_inputs(0x100, 0x2000_0001)),
            ResetOrData::Data([
                CompressionInput::default(),
                prepared_input(1, 0x2100_0002, 0x101),
                prepared_input(2, 0x2200_0002, 0x101),
            ]),
            ResetOrData::Data([
                prepared_input(0, 0x2000_0003, 0x102),
                CompressionInput::default(),
                prepared_input(2, 0x2200_0003, 0x102),
            ]),
            ResetOrData::Data([
                prepared_input(0, 0x2000_0004, 0x103),
                prepared_input(1, 0x2100_0004, 0x103),
                CompressionInput::default(),
            ]),
            ResetOrData::Reset,
        ]);

        // Run well beyond two additional wraps after reset. Each lane has a
        // distinct bubble cadence, so valid isolation is visible cycle by cycle.
        for cycle in 0..17_u32 {
            let input = core::array::from_fn(|lane| {
                let valid = match lane {
                    0 => cycle % 5 != 1,
                    1 => cycle % 4 != 2,
                    2 => cycle % 3 != 0,
                    _ => false,
                };
                if valid {
                    prepared_input(
                        lane,
                        0x3000_0000
                            ^ cycle
                            ^ (u32::try_from(lane).expect("lane fits u32") * 0x0100_0000),
                        0x200 + cycle,
                    )
                } else {
                    CompressionInput::default()
                }
            });
            events.push(ResetOrData::Data(input));
        }
        events.extend(std::iter::repeat_n(
            ResetOrData::Data([CompressionInput::default(); SMALL_LANES]),
            SMALL_ROUNDS,
        ));
        events
    }

    #[test]
    fn small_farm_rhdl_and_iverilog_preserve_asymmetric_lane_isolation() -> Result<(), RHDLError> {
        let farm = CompressionFarm::<SMALL_LANES, SMALL_ROUNDS, SMALL_ADDRESS_BITS>::default();
        let events = small_farm_events();
        let observed = observed_lane_outputs(&farm, &events);

        for (lane, lane_outputs) in observed.iter().enumerate() {
            assert_eq!(
                lane_outputs,
                &expected_lane_outputs(&events, lane, SMALL_ROUNDS),
                "lane {lane} changed latency, data, tag, or valid behavior"
            );
            assert!(lane_outputs.iter().all(|(_, output)| {
                usize::try_from(word_u32(output.tag) >> 24).expect("lane byte fits usize") == lane
            }));
        }
        assert_ne!(observed[0].len(), observed[2].len());
        assert!(events.len() > 4 * SMALL_ROUNDS);

        let test_bench = farm
            .run(events.into_iter().clock_pos_edge(10))
            .collect::<SynchronousTestBench<_, _>>();
        test_bench
            // `clock_pos_edge` records multiple timed cases per issue cycle.
            // Eighteen cases place comparison after the resetless four-stage
            // datapaths and registered memory outputs have all become known.
            .rtl(&farm, &TestBenchOptions::default().skip(18))?
            .run_iverilog()?;
        Ok(())
    }

    #[test]
    fn small_replicated_farm_matches_the_ordinary_farm_and_software_oracle() {
        let ordinary = CompressionFarm::<SMALL_LANES, SMALL_ROUNDS, SMALL_ADDRESS_BITS>::default();
        let replicated =
            ReplicatedCompressionFarm::<SMALL_LANES, SMALL_ROUNDS, SMALL_ADDRESS_BITS>::default();
        let events = small_farm_events();
        let ordinary_observed = observed_lane_outputs(&ordinary, &events);
        let replicated_observed = observed_lane_outputs(&replicated, &events);

        assert_eq!(replicated_observed, ordinary_observed);
        for (lane, lane_outputs) in replicated_observed.iter().enumerate() {
            assert_eq!(
                lane_outputs,
                &expected_lane_outputs(&events, lane, SMALL_ROUNDS),
                "replicated lane {lane} diverged from the independent round model"
            );
        }
    }

    #[test]
    fn small_replicated_farm_lowers_one_lane_module_and_three_instances() -> Result<(), RHDLError> {
        let farm =
            ReplicatedCompressionFarm::<SMALL_LANES, SMALL_ROUNDS, SMALL_ADDRESS_BITS>::default();
        let descriptor = farm.descriptor("sha256_replicated_compression_farm".into())?;
        let hdl = descriptor.hdl()?.modules.pretty();

        assert_eq!(
            hdl.matches("module sha256_replicated_compression_farm_lanes_prototype(")
                .count(),
            1
        );
        for index in 0..SMALL_LANES {
            assert_eq!(
                hdl.matches(&format!(
                    "sha256_replicated_compression_farm_lanes_prototype c{index}("
                ))
                .count(),
                1,
                "replicated lane instance c{index} must appear exactly once"
            );
        }
        assert_eq!(hdl.matches("reg [255:0] mem[3:0]").count(), 1);
        Ok(())
    }

    #[test]
    fn full_three_lane_farm_matches_software_for_more_than_two_wraps() {
        // Three copies of the 64-stage simulation state exceed libtest's
        // default worker-stack allocation before the first modeled cycle. The
        // stack override is host-test scaffolding only; it is not part of the
        // RHDL circuit or generated RTL.
        std::thread::Builder::new()
            .name("sha256-full-three-lane-rhdl".into())
            .stack_size(64 * 1024 * 1024)
            .spawn(run_full_three_lane_farm_test)
            .expect("spawn full-farm RHDL test with an explicit stack")
            .join()
            .expect("full-farm RHDL test thread must not panic");
    }

    fn run_full_three_lane_farm_test() {
        let mut events = vec![ResetOrData::Reset];
        events.extend((0..7_u32).map(|cycle| {
            ResetOrData::Data(core::array::from_fn(|lane| {
                prepared_input(lane, 0x4000_0000 ^ cycle, cycle)
            }))
        }));
        events.push(ResetOrData::Reset);

        // 137 post-reset issue cycles exceed two complete 64-entry pointer
        // wraps while retaining independent valid patterns in all three lanes.
        for cycle in 0..137_u32 {
            let input = core::array::from_fn(|lane| {
                let valid = match lane {
                    0 => cycle % 11 != 7,
                    1 => cycle % 7 != 3,
                    2 => cycle % 5 != 1,
                    _ => false,
                };
                if valid {
                    prepared_input(
                        lane,
                        0x5000_0000
                            ^ cycle.rotate_left(u32::try_from(lane).expect("lane fits u32")),
                        0x1000 + cycle,
                    )
                } else {
                    CompressionInput::default()
                }
            });
            events.push(ResetOrData::Data(input));
        }
        events.extend(std::iter::repeat_n(
            ResetOrData::Data([CompressionInput::default(); PERFORMANCE_FARM_LANES]),
            ROUND_COUNT,
        ));

        let farm = ThreeLaneCompressionFarm::default();
        let observed = observed_lane_outputs(&farm, &events);
        for (lane, lane_outputs) in observed.iter().enumerate() {
            assert_eq!(
                lane_outputs,
                &expected_lane_outputs(&events, lane, ROUND_COUNT),
                "full lane {lane} diverged from the independent SHA-256 model"
            );
            assert!(lane_outputs.len() > FULL_LANE_ADDRESS_BITS * 8);
            assert!(lane_outputs.iter().all(|(_, output)| {
                usize::try_from(word_u32(output.tag) >> 24).expect("lane byte fits usize") == lane
            }));
        }
    }

    #[test]
    fn checked_small_farm_generator_contains_three_independent_memories() -> Result<(), RHDLError> {
        let hdl =
            compression_farm_checked_verilog::<SMALL_LANES, SMALL_ROUNDS, SMALL_ADDRESS_BITS>()?;
        assert!(hdl.contains("module sha256_compression_farm"));
        assert_eq!(hdl.matches("reg [255:0] mem[3:0]").count(), SMALL_LANES);
        Ok(())
    }

    #[test]
    #[ignore = "explicit full-hierarchy render gate; excluded from routine unit tests"]
    fn full_replicated_farm_generation_only_unchecked_render() -> Result<(), RHDLError> {
        let hdl = try_full_three_lane_farm_generation_only_unchecked_verilog()?;
        assert!(hdl.contains("module sha256_compression_farm_3x64"));
        assert_eq!(hdl.matches("reg [255:0] mem[63:0]").count(), 1);
        assert_eq!(
            hdl.matches("module sha256_compression_farm_3x64_lanes_prototype(")
                .count(),
            1
        );
        for index in 0..PERFORMANCE_FARM_LANES {
            assert_eq!(
                hdl.matches(&format!(
                    "sha256_compression_farm_3x64_lanes_prototype c{index}("
                ))
                .count(),
                1
            );
        }
        Ok(())
    }
}