RHDL and generated Verilog

Cryptographic datapaths are authored in Rust against pinned RHDL commit c99d5cc53269a247bbc675d0fbd766991d409f56. Generated Verilog is a deterministic artifact, not the place to implement or optimize the algorithm.

Why the production bundle is modular

Lowering a complete 64-stage SHA-256 lane and the full signer graph in one process requires a large host-memory peak. The production gate instead:

1. lowers the exact full compression lane;
2. lets that process exit and release its address space;
3. lowers a typed signer skeleton with one unresolved lane prototype;
4. checks the reachable module graph and cardinality;
5. links the lane definition and skeleton without editing either; and
6. asks an external parser and simulator to elaborate the complete bundle.

The vendored RHDL patch adds a narrow external-module path and a repeated synchronous hierarchy primitive. It does not weaken the checked public HDL entry point, and it contains no cryptographic algorithm rewrite.

Evidence consequences

• A descriptor or rendered module is source-structure evidence.
• Parser acceptance is generated-source elaboration evidence.
• A self-checking Verilator trace is finite generated-RTL equivalence evidence.
• None of those reports mapped LUTs, registers, BRAM, URAM, DSPs, timing, route, or a card measurement.

The generator manifest binds source identity, profile, target, widths, file lengths, checksums, and validation boundary. A production evidence bundle also binds lowering logs, testbench, simulator logs, and the exact PASS marker.