Known gaps
The following boundaries remain open until a directly supporting evidence record is added:
Current U280 status
The generated evidence matrix is canonical. Its current hardware rows remain pending:
| Gate | Status | Claim still unavailable |
|---|---|---|
| 250 MHz / 4.000 ns synthesis | Pending | Exact U280 mapping, resources, and estimated timing |
| 250 MHz / 4.000 ns route | Pending | Completely routed timing closure at the normalization clock |
| 300 MHz / 3.333 ns synthesis | Pending | Exact U280 mapping and estimated timing at the clock goal |
| 300 MHz / 3.333 ns route | Pending | Completely routed timing closure at the clock goal |
| Programmed-card execution | Pending | Card correctness, achieved clock, and measured throughput |
The preserved 6801a66-41fe7ba3-20260715T1103PDT stage is unlaunchable and
forensic only; it cannot fill any row. A future attempt must begin with a fresh
schema-v2 baseline stage as described by the
U280 evidence workflow.
Other open boundaries
- The SHA-256 verifier lacks linked generated-RTL equivalence evidence.
- U280 synthesis and routed timing must remain attached to the exact staged RTL and constraint that produced them.
- A routed OOC crypto top is not a Vitis shell or card result.
- Card execution must validate every returned signature before reporting measured throughput.
- Arbitrary output backpressure is not covered by the current always-ready sustained signer benchmark.
- Four-state unknown propagation and formal protocol proofs are not supplied by the two-state Verilator traces.
- Physical side-channel behavior and complete stale-state scrubbing have not been audited.
- No active legacy Keccak hardware verifier is implemented.
- External source and contribution links are omitted until a public repository is verified, and no private vulnerability-reporting channel is currently advertised.
An open gap is not a failed claim. It is a boundary the project refuses to hide.