pub fn round_pipeline_unchecked_verilog<const ROUNDS: usize>() -> Result<String, RHDLError>where
W<ROUNDS>: BitWidth,Expand description
Emits a registered round-pipeline prefix without RHDL’s Icarus syntax check.
This entry point exists because Icarus Verilog 13 cannot lex the monolithic
function emitted for the complete 64-stage specialization: its scanner
reports an input-buffer overflow. Returning this string proves only that
RHDL constructed and rendered the descriptor. It is not evidence that
the output parsed, simulated, synthesized, or is equivalent to the RHDL
model. Use round_pipeline_verilog whenever the specialization is small
enough for the built-in checker, and gate a complete lane with Verilator and
Vivado before treating it as synthesis-ready.
§Errors
Returns an error if the specialization is invalid or RHDL cannot compile, lower, or render the synchronous circuit.