Generate and validate RTL

rhdl-gen is the deterministic boundary between Rust/RHDL and generated Verilog. It does not synthesize or execute hardware.

Registry and quick checks

cargo run --locked -j1 -p rhdl-gen -- list
cargo run --locked -j1 -p rhdl-gen -- generate sha256-round --output generated
cargo run --locked -j1 -p rhdl-gen -- check

The registry keeps profile and top identity explicit. Generated files have adjacent manifests with source revision, dirty state, profile, target, checksum, and evidence tier.

Complete SHA lane and farm

The opt-in check --full gate renders complete SHA structures and uses Verilator for lint, elaboration, and self-checking arithmetic traces. Accepted warnings remain recorded; -Wno-fatal is not a warning-clean claim.

Production signer

The check --signer-full gate lowers the lane and unresolved signer skeleton in separate processes, validates the reachable hierarchy, links exact read-only sources, and runs a finite self-checking trace. Preserve the output only when an evidence record needs its manifests and logs.

The separate signer-throughput command consumes a previously successful finite-equivalence bundle. It revalidates that chain and measures a longer always-ready trace without re-lowering or editing RTL.

See the rhdl-gen API and generated evidence matrix for the current exact command and boundaries.