Struct NoResetDff 

pub struct NoResetDff<T: Digital> { /* private fields */ }

A positive-edge-triggered, resetless register for datapath storage.

NoResetDff<T> deliberately ignores the reset member of RHDL’s mandatory [ClockReset] interface. The emitted HDL contains only a clock extraction and an unconditional nonblocking assignment on the rising edge. It contains neither an initialization block nor a reset branch.

The value before the first rising edge is unspecified. A design must pair this register with separately reset validity or allocation state and must not consume the output until that state says the value is valid.

This is a native RHDL synchronous component. Its Verilog is constructed with RHDL’s HDL AST in the same way as the pinned rhdl-fpga DFF; generated RTL is never textually rewritten.

Implementations

impl<T: Digital> NoResetDff<T>

pub const fn new() -> Self

Constructs a resetless register.

Trait Implementations

impl<T: Clone + Digital> Clone for NoResetDff<T>

fn clone(&self) -> NoResetDff<T>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<T: Debug + Digital> Debug for NoResetDff<T>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<T: Default + Digital> Default for NoResetDff<T>

fn default() -> NoResetDff<T>

Returns the “default value” for a type.

impl<T: PartialEq + Digital> PartialEq for NoResetDff<T>

fn eq(&self, other: &NoResetDff<T>) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl<T: Digital> Synchronous for NoResetDff<T>

type S = NoResetDffState<T>

The simulation state type. This type is used to represent the internal state of the circuit during simulation. It must be PartialEq and Clone. It holds whatever state is needed to compute the output of the circuit given it’s input. This state is typically auto-derived by the Synchronous derive macro, and it’s typically a struct containing the states of all the subcircuits, along with their last know outputs.

fn init(&self) -> Self::S

Initialize the simulation state. This method returns the initial state of the circuit for simulation. This is typically auto-derived by the Synchronous derive macro, and it typically initializes the states of all the subcircuits to their initial states.

fn sim( &self, clock_reset: ClockReset, input: Self::I, state: &mut Self::S, ) -> Self::O

Simulate the circuit given it’s input, clock reset, and current state.

fn descriptor( &self, scoped_name: ScopedName, ) -> Result<Descriptor<SyncKind>, RHDLError>

Provides run time reflection of the circuit.

fn children( &self, _parent_scope: &ScopedName, ) -> impl Iterator<Item = Result<Descriptor<SyncKind>, RHDLError>>

Iterate over the child circuits of this circuit.

impl<T: Digital> SynchronousDQ for NoResetDff<T>

type D = ()

The type of the internal data input to the children of the circuit.

type Q = ()

The type of the internal data output from the children of the circuit.

impl<T: Digital> SynchronousIO for NoResetDff<T>

type I = T

The type of the input to the circuit.

type O = T

The type of the output from the circuit.

type Kernel = NoSynchronousKernel<ClockReset, T, (), (T, ())>

The type of the kernel function used to compute the output and feedback. The kernel function must be a synthesizable function that takes a clock and reset signal, the input signal, and the feedback signal Q, and produces the output signal and feedback signal D.

impl<T: Copy + Digital> Copy for NoResetDff<T>

impl<T: Digital> StructuralPartialEq for NoResetDff<T>