Struct InlineCompressionLane 

pub struct InlineCompressionLane<const ROUNDS: usize, const ADDRESS_BITS: usize>;

Copyable type-level adapter for an inline CompressionLane.

Pinned RHDL derives place the injected child type itself in the generated Copy + PartialEq bounds for a parent’s D/Q records, even though those records contain only the child’s digital input and output. The concrete CompressionLane carries elaboration configuration and is intentionally not Copy. This zero-sized adapter preserves the exact native lane state, simulation, and checked descriptor while satisfying that conservative derive bound. It does not add a hardware wrapper or alter the emitted lane hierarchy.

Trait Implementations

impl<const ROUNDS: usize, const ADDRESS_BITS: usize> Clone for InlineCompressionLane<ROUNDS, ADDRESS_BITS>

fn clone(&self) -> InlineCompressionLane<ROUNDS, ADDRESS_BITS>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<const ROUNDS: usize, const ADDRESS_BITS: usize> Debug for InlineCompressionLane<ROUNDS, ADDRESS_BITS>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<const ROUNDS: usize, const ADDRESS_BITS: usize> Default for InlineCompressionLane<ROUNDS, ADDRESS_BITS>

fn default() -> InlineCompressionLane<ROUNDS, ADDRESS_BITS>

Returns the “default value” for a type.

impl<const ROUNDS: usize, const ADDRESS_BITS: usize> PartialEq for InlineCompressionLane<ROUNDS, ADDRESS_BITS>

fn eq(&self, other: &InlineCompressionLane<ROUNDS, ADDRESS_BITS>) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl<const ROUNDS: usize, const ADDRESS_BITS: usize> Synchronous for InlineCompressionLane<ROUNDS, ADDRESS_BITS>

where W<ROUNDS>: BitWidth, W<ADDRESS_BITS>: BitWidth,

type S = <CompressionLane<ROUNDS, ADDRESS_BITS> as Synchronous>::S

The simulation state type. This type is used to represent the internal state of the circuit during simulation. It must be PartialEq and Clone. It holds whatever state is needed to compute the output of the circuit given it’s input. This state is typically auto-derived by the Synchronous derive macro, and it’s typically a struct containing the states of all the subcircuits, along with their last know outputs.

fn init(&self) -> Self::S

Initialize the simulation state. This method returns the initial state of the circuit for simulation. This is typically auto-derived by the Synchronous derive macro, and it typically initializes the states of all the subcircuits to their initial states.

fn sim( &self, clock_reset: ClockReset, input: Self::I, state: &mut Self::S, ) -> Self::O

Simulate the circuit given it’s input, clock reset, and current state.

fn descriptor( &self, scoped_name: ScopedName, ) -> Result<Descriptor<SyncKind>, RHDLError>

Provides run time reflection of the circuit.

fn children( &self, _parent_scope: &ScopedName, ) -> impl Iterator<Item = Result<Descriptor<SyncKind>, RHDLError>>

Iterate over the child circuits of this circuit.

impl<const ROUNDS: usize, const ADDRESS_BITS: usize> SynchronousDQ for InlineCompressionLane<ROUNDS, ADDRESS_BITS>

where W<ROUNDS>: BitWidth, W<ADDRESS_BITS>: BitWidth,

type D = ()

The type of the internal data input to the children of the circuit.

type Q = ()

The type of the internal data output from the children of the circuit.

impl<const ROUNDS: usize, const ADDRESS_BITS: usize> SynchronousIO for InlineCompressionLane<ROUNDS, ADDRESS_BITS>

where W<ROUNDS>: BitWidth, W<ADDRESS_BITS>: BitWidth,

type I = CompressionInput

The type of the input to the circuit.

type O = CompressionOutput

The type of the output from the circuit.

type Kernel = NoSynchronousKernel<ClockReset, CompressionInput, (), (CompressionOutput, ())>

The type of the kernel function used to compute the output and feedback. The kernel function must be a synthesizable function that takes a clock and reset signal, the input signal, and the feedback signal Q, and produces the output signal and feedback signal D.

impl<const ROUNDS: usize, const ADDRESS_BITS: usize> Copy for InlineCompressionLane<ROUNDS, ADDRESS_BITS>

impl<const ROUNDS: usize, const ADDRESS_BITS: usize> Eq for InlineCompressionLane<ROUNDS, ADDRESS_BITS>

impl<const ROUNDS: usize, const ADDRESS_BITS: usize> StructuralPartialEq for InlineCompressionLane<ROUNDS, ADDRESS_BITS>