Crate rhdl_primitives 

Reusable synthesis-aware RHDL primitives for the HashSigs datapaths. Wide cryptographic pipelines do not need a known value in every data register after reset. Their valid bits provide the ownership boundary: data is only observed when the corresponding valid bit is set. Resetting thousands of otherwise don’t-care data bits wastes routing and can prevent FPGA register packing, so this crate provides NoResetDff. Control state must continue to use an explicitly reset primitive such as [rhdl_fpga::core::dff::DFF].

Structs

NoResetDff

A positive-edge-triggered, resetless register for datapath storage.