Expand description
Complete streaming compression-lane implementation. Complete, one-block-per-cycle SHA-256 compression lane.
A lane combines the registered round pipeline with a circular synchronous
memory holding the original 256-bit chaining values. At cycle t it writes
the accepted chaining value at pointer p. At cycle t + ROUNDS - 1 it
reads address p; the memory’s registered output and the round token are
both visible at cycle t + ROUNDS, where feed-forward is combinational.
ROUNDS must equal 2^ADDRESS_BITS. Consequently the current write address
and the read address (write + 1) are always distinct for supported lanes,
avoiding the pinned [rhdl_fpga::core::ram::synchronous::SyncBRAM]’s explicitly undefined same-address
read/write behavior. The pointer advances through valid tokens and bubbles,
because alignment is measured in cycles rather than accepted-token count.
All three-lane figures in this module are arithmetic projections. Physical block-RAM mapping, three-lane integration, resources, and timing remain synthesis or implementation gates.
Structs§
- Compression
Input - Prepared input accepted by a compression lane on every rising edge.
- Compression
Lane - Fully occupied SHA-256 compression pipeline with circular base-state delay.
- Compression
Output - Feed-forward result produced by a compression lane.
- External
Full Compression Lane - Behavioral full lane with an unresolved external HDL implementation.
- Inline
Compression Lane - Copyable type-level adapter for an inline
CompressionLane.
Constants§
- AVOIDED_
CHAINING_ DELAY_ FFS - Flip-flops a naïve 64-stage chaining-value delay would add per lane.
- FULL_
LANE_ ADDRESS_ BITS - Address width of the complete 64-round lane’s chaining-value memory.
- FULL_
LANE_ CHAINING_ STORAGE_ BITS - Logical storage bits in one complete lane’s chaining-value memory.
- FULL_
LANE_ DELAY_ DEPTH - Number of entries in the complete lane’s circular chaining-value memory.
- SHA256_
COMPRESSION_ LANE_ MODULE - Canonical module name of the separately generated complete compression lane.
- THREE_
LANE_ AVOIDED_ CHAINING_ DELAY_ FFS - Projected flip-flops avoided by three circular chaining memories.
- THREE_
LANE_ CHAINING_ STORAGE_ BITS - Projected logical chaining-memory bits for three complete lanes.
Functions§
- compression_
lane_ checked_ verilog - Emits and Icarus-checks a power-of-two lane specialization.
- compression_
lane_ kernel - Connectivity and feed-forward kernel for
CompressionLane. - try_
full_ compression_ lane_ unchecked_ verilog - Renders the full lane while deliberately bypassing its final Icarus check.
Type Aliases§
- Full
Compression Lane - Complete 64-round, 64-entry compression lane.