Reading paths

New Rust/RHDL contributor

1. Make a first change in 30 minutes
2. WOTS+ in this project
3. Active system map
4. RHDL and generated Verilog
5. Source map
6. Test from leaf to top

Cryptography or protocol reviewer

1. Two incompatible profiles
2. One-time-key lifecycle
3. Streams and packed interfaces
4. SHA-only hardware verifier
5. Security policy

FPGA, timing, or resource contributor

1. Production signer
2. Hash engines
3. Read throughput correctly
4. Generate and validate RTL
5. U280 evidence workflow

Evidence auditor

1. Evidence ladder
2. Generated evidence matrix
3. The source evidence record linked by the matrix
4. The exact artifact manifest and checksums named by that record

No reading path treats a normalized simulator rate as measured FPGA throughput.